Table of contents5 CPU Externals 5.1 Parallel buses 5.1 Parallel buses 5.1 Parallel buses 5.1.1 Parallel buses - timing diagram 5.1.2 Parallel buses - control 5.1.2 Parallel buses - control 5.1.2 Parallel buses - control 5.1.3 Parallel buses - multiplex 5.1.4 Parallel buses - clocking 5.1.5 Parallel buses - bandwidth 5.3 I/O 5.1.6 Parallel buses - DMA 5.1.7 Parallel buses - example 5.2 Serial buses 5.3 I/O 5.4 Interrupts 5.4.1 Interrupts - vectors 5.4.1 Interrupts - vectors 5.4.2 Interrupts - priorities 5.4.2 Interrupts - priorities 5.4.3 Interrupts - ISR 5.4.3 Interrupts - ISR 5.4.4 Interrupts - example 5.4.4 Interrupts - example |
Author: Ian McLoughlin E-mail: asian@ntu.edu.sg Homepage: http://www.lintech.org/CE302/ Further information: Best viewed with |
