Q1. Could you please explain on Blackboard system.

It is not required to know this in CE302: I only mentioned it for completeness.  If you are studying parallel processing where many different CPUs work together, then it is a method of allocating parts of the task (or program) to the different processors.  You only need to know more than this if you are interested in parallel processing for your FYP or for general interest.
 

Q2. What is MIP stand for?

MIPS actually stands for Millions of Instructions Per Second.  This is a (not very good) measure of how powerful a computer is: how many MIPS it can execute.  The reason the measure is no good is that different instructions can do different things.  1 million floating point adds per second is extremely fast, but 1 million fixed point adds is very slow.  For this reason the MIPS figures for most processors is an average of the maximum execution speed of each instruction in the instruction set.

MIPS is also the name of a company, and so the MIPS R2000 and R3000 are processors (that we simulate in the CE302 lab).
 

Q3. How do you obtain the values for the examples for Excess-n?
            10101110B=47d and 01010010B= - 45d

I'll be giving some examples of the excess-n representation in the lecture and also in the tutorials.

But for now: unsigned binary number 10101110 would have a value of 174 in decimal.  If the number is excess-127 then the value stored is actually 174-127=47.   So you can see that the actual number stored is found by working out what is the decimal value of that bitpattern (as an unsigned binary number) and then  subtracting 127 from this (for excess-127).
 

Q4.  Can the L registers of DAG (Dedicated Address Generation) hold a negative value
(i.e. negative displacement)?
For example, L1= -20, I1=100, M1=1
After this AX0= DM(I1, M1)
 I1=100+1-20=81
 Am I right?

This example looks reasonable however;

1. someone borrowed my ADSP2181 data book so I can't check exactly
what the behavour is;
2. you definitely don't need to know *exactly* how the ADSP2181
behaves.  What you need to know is that some method of h/ware
addressing like this exists, roughly what hardware is needed and
roughly how to use it in software.  Most importantly, *why* it is
used and *how* it improves the situation.

Q5.  On pg 3.2, section 3.1.7., there is a question :" Can the register usage limitations tell us
how many data buses are inside the two CPUs?" 
In your lecture, you mentioned "Yes". But why?

In some ways, if one functional unit can only use a subset of the registers
available then you assume a different internal architecture (not RISC-like).
Continuing - if the ALU result register can feed the MUL input but not the
shifter input, then that result register is probably not connected to a common
results bus.

You can use this sort of methodology to build up a picture of the internal
connections.   Note that this picture may never be exact - it can just start to give
us a 'feel' for what's inside this particular CPU.

Q6. In one of your lectures, you went through a question on IEEE754 floating pt  number system.
 The confusion arises when asked to find the smallest normalised number & smallest denormalised
number representable.
In your lecture, the answer given was smallest positive number.
 Do we always assume smallest number means smallest positive number and not
smallest negative number?

In general, I would make it clear either by stating what is required of by
giving a hint such as saying "unsigned".

Largest means biggest positive.
To count negative numbers also I would say "largest magnitude".

Q7. With regards to CPU testing, what was the concept behind the bit walk?

The bit walk is something like
0000
0001
0010
0100
1000

So we can, in turn, switch each bit ON or OFF and check for;
1. short circuits between adjacent pins
2. stuck-at-zero faults
3. stuck-at-one faults
 

Q8. You've mentioned multithreading with respect to shadow registers. Could you explain what it is?

Multithreading is a method of multitasking.  You don't actually need
to know the full details of this for CE302.  It is a way of having
different 'contexts' running simultaneously where your CPU can
switch between contexts, execute a few instructions, and then switch
back.  Each context could be a different program, or a different
thread of the same program (i.e. in languages like POSIX 'C', java
and ada you can have different subroutines in your program running
simultaneously).

Shadow registers can be used (and are used on the UltraSPARC for
example) to give each context its own set of registers (otherwise you
would have to context save and restore each register you use every
time you switch - making the context switch very 'expensive' in
terms of CPU time).
 

Q9. Is chapter 6 of the lecture notes examinable?

Not directly.  The techniques used illustrate concepts that were introduced
in parts 1,2 3, 4 & 5.  These concepts are examinable.

Q10. Which past year paper should we refer to? (which paper was set by you).

November 1999
May 2000

Q11. Given a reservation table for a pipeline processor, must we able to make
the state diagram for that pipeline? If yes, how?

No.

Q12. What does minimum average latency mean?

Concentrate on the meanings of throughput, and speedup.

Q13. How is the RAM look up table for MMU organized? I have found two ways:
 direct and associative? Could you please explain the advantages and disadvantages of the two?

This level of detail is unecessary.  It is applying cache concepts to the MMU.
As long as you understand the concepts for cache, that is OK. And that is definitely
more important.

Q14.  When we use LFU as caching algorithm, do we count the number of the cache
line used, or the cache entry? -> i.e. do we need to reset the counter in the cache line
everytime we load a new one?

Of course you are considering individual data items.  i.e. how long has it been
since the line caching address X has been accessed?  If it is a long time, then
this cache line can be reused.

This means that yes, you need to reset the counter for a line whenever you load
new data into that cache line.