1. Design hardare to multiply any number (stored in a register) by a value between 1 and 10. Draw a block diagram but ignore control logic. You are constrained to use exactly 2 adders and 2 shifters.
The shifter can only <<1. You have 2 registers. 1 for the multiplicand and 1 for the result (the multiplier of 1 to 10 is specified as part of the instruction).

2. Pipeline the design above, this time only a single adder and a single shifter.

3. Draw a reservation table for the pipeline.

4. Redesign the MESI protocol and redraw the MESI state diagram for a non-shared system (i.e. one in which there is only a single CPU).

5. Consider a single instruction computer (SIC) - yes this is possible! It has 1 instruction, the conditional move:

CMOVE   destination, source

(a) how can it perform functions (i.e. suggest an internal structure to allow standard CPU functions to be performed).
(b) what are the advantages and disadvantages of such a processor, considering complexity and efficiency

6. A new CPU is being designed that has single-address instructions and 8 bit words (i.e. each instruction specifies an operation, and an address for a single operand). There are 3 bits available in the opcode field, allowing only 8 instructions.
(a) Which 8 instructions would you choose - assuming a conventional architecture (i.e. not something like in Q5).
(b) are there any operations that cannot be performed?

7. Consider the advantages and disadvantages of the two different two-phase clocking schemes: two-phase quadrature clock and two-phase non-overlapping clock.

_|~~~|___|~~~|___|~~~|___|~~~|___

___|~~~|___|~~~|___|~~~|___|~~~|_

(two-phase quadrature clocks above)

_|~|___|~|___|~|___|~|___|~|___|~
____|~|___|~|___|~|___|~|___|~|__

(two-phase non-overlapping clocks above)

8. The standard ARM instruction format uses 4 bits of each 32-bit instruction as a condition field. This is because every ARM instruction can be executed conditionally if required.
What proportion of instructions should be executed conditionally to ensure that the processor as it currently stands, is more efficient in terms of code size, than a new processor with those bits omitted (i.e. one that only has the standard conditional branch).
If such a processor existed, compare its likely processing performance with the existing ARM design.

9. Most processors do not allow an interrupt to occurr DURING an instruction execution (instead you need to wait for that instruction to end before the interrupt can be begun).
Why is that not usually allowed?
What class of processors suffer from extremely long interrupt service latencies?
What features of processors cause excessively large interrupt penalties to their data throughput?