MESI Cache Coherency Protocol

If this scheme is used in a shared-memory multi-processor system, then each CPU has its own cache. Each cache has the usual line number and a tag, but the valid/clean flags are replaced with one of the states shown; invalid, modified, exclusive, shared.

All cache lines are set to invalid after reset. It means that the data in that cache line is not correct, and doesn't reflect any real memory locations.

If your CPU then access RAM then that RAM value will be loaded into cache, and the cache will send that data to the CPU. In that case, the cache line used will be placed into the exclusive state.

If another CPU then reads the same address from shared memory, your cache entry will now be set to shared.

Finally, if your CPU writes a value to cache (and the caching algorithm doesn't write back to RAM) then that cache line will have a state of modified. At the same time, if any of the caches in other CPUs are accessing the same location, their lines (i.e. in the other CPUs) will be set to invalid.

The state diagram shown above shows all the possible transitions in the MESI scheme.